{\rtf1\ansi\ansicpg1252\uc0\deff0{\fonttbl {\f0\fswiss\fcharset0\fprq2 Arial;} {\f1\froman\fcharset2\fprq2 Symbol;}} {\colortbl;\red0\green0\blue255;\red255\green255\blue255;\red0\green0\blue0;} {\info{\*\hlinkbase e:\\Medaps\\CA01_Generate\\export\\CA01_ENG_INT_IK_05102004\\rtf\\}{\comment TX_RTF32 8.0.300.500}} \deftab708\paperw15309\paperh16840\margl1134\margt1134\margr3430\margb1338\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60\plain\f0\fs14\b\cf1 System\cell SIJECT\~16CI\~16i\cell SIJECT\~16CI\~16iP\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60\plain\f0\fs14 PLC module\cell 314\cell 314C-2DP\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Programming\cell SIMATIC STEP 7\cell SIMATIC STEP 7\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Memory capacity\cell 128 KB\cell 520 KB\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Program memory\cell 48 KB\cell 400 KB\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Timers\cell 128\cell 256\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Counters\cell 64\cell 256\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Digital inputs (24\~V DC)\cell 31\cell 31\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 High-speed counter (1\~kHz)\cell 1\cell 1\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Digital outputs (2\~A)\cell 40\cell 40\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Short-circuit-proof\cell Yes\cell Yes\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Thermocouple inputs (16\~bits)\cell 8\cell 8\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Linear scale (1\~to\~10\~kOhm; 12\~bits)\cell 4\cell 4\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 High-speed analog signals (0\~to\~10\~V; 14-bit resolution)\cell \'96\cell 2 (X305)\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Proportional valve (\'b110\~V; 12\~bits)\cell 4\cell 4\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Proportional valve (+24\~to\~+38\~V; 0.75\~to 2\~A; 12\~bits)\cell 2 (X306)\cell \'96\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 OP interface (serial)\cell 1\cell 1\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 MPI interface\cell 1\cell 1\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 I/O bus interface\cell 1\cell 1\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 PROFIBUS DP interface\cell -\cell 1\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 MMC card\cell 1\cell 1\cell\intbl\row\pard\trowd\trgaph70\trleft0\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx4276\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx7235\clbrdrl\brdrs\brdrw5\clbrdrt\brdrs\brdrw5\clbrdrr\brdrs\brdrw5\clbrdrb\brdrs\brdrw5\cellx10194\pard\widctlpar\intbl\pard\intbl\sb60\sa60 Power supply\cell 24 V DC\cell 24 V DC\cell\intbl\row\pard\pard\sb100\par }